1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory for storing data by injecting a charge into a stacked-layer film having a charge storage ability.
2. Description of the Related Art
In the past, a non-volatile memory injecting a charge into a stacked-layer film having a charge storage ability under predetermined voltage conditions desirably has used a high voltage for write and erase operations. Further, such a non-volatile memory has sometimes been combined with a logic circuit on the same IC. Below, such an IC is referred to as a “combination non-volatile memory”. In a combination non-volatile memory, a voltage higher than the voltage for driving the logic circuit is generated for operating the non-volatile memory, so high withstand (torelance) voltage devices (devices able to operate at a high voltage) are desirable in addition to the logic transistors and other devices able to operate at a standard power voltage.
This means it is desirable to form not only the non-volatile memory, but also the high withstand voltage devices on the same IC in the wafer production process of a combination non-volatile memory. This leads to an increase of the production steps and an increase of the number of masks. Incidentally, in an IC mounting the currently mainstream floating gate (FG) type memory devices in combination, in practice about a half of the masks added to the masks required for the standard logic process are for the high withstand voltage devices. Accordingly, when establishing a combination process of combining a non-volatile memory with an existing logic process, if lowering the voltage of the memory devices to an extent that they may operate with the standard provided voltage (logic use power voltage etc.), high withstand voltage transistors become unnecessary and the number of steps for combination and the increase of the number of additional masks may be suppressed. In this way, lowering the operating voltage is an important issue in combination non-volatile memories.
The rise of the threshold voltage when raising the threshold voltage from the level of the non-write state to the level of the write state at the time of a write operation is usually called as a “window”. In a memory device, the window becomes small during long term storage at a high temperature and further while write and erase operations are repeated many times. For this reason, when reading whether or not a write operation was effectively performed according to the difference of the amount of channel current when applying predetermined voltage conditions enabling a memory transistor to be turned ON, it is desirable to make the window immediately after the write operation large enough for maintaining the long term reliability of electrical characteristics while securing the lowest voltage margin necessary for a read operation. However, if the operating voltage is lowered, the window becomes proportionally smaller. The fact that the window immediately after the write operation becomes smaller together with the operating voltage is becoming an obstacle (hurdle) to lowering the voltage. Therefore, various means for reducing the operating voltage in combination non-volatile memories are being proposed from a variety of viewpoints (refer to for example Japanese Unexamined Patent Publication (Kokai) No. 2001-102553).
Turning now to the disadvantage to be solved by the invention, Japanese Unexamined Patent Publication (Kokai) No. 2001-102553 tries to reduce the absolute value of the operating voltage by supplying the operating voltage to the memory devices of a combination non-volatile memory divided into a negative voltage and a positive voltage, but does not study the method of raising the threshold voltage of the memory devices to the maximum by a voltage corresponding to the prepared power voltage.